1. Field of the Invention
This invention relates to clock systems employed to synchronize or time the operation of high speed central processing units. More particularly, this invention relates to logic circuits for generating a plurality of new clock signals which are phase related to the master clock of the central processing unit and for selecting one of the new clock signals to be employed as the master clock for the central processing unit. The new clock selected to be used in place of the master clock is the first of the new clock signals capable of synchronizing with an incoming asynchronous control signal.
2. Discussion of the Prior Art
It is well known that high speed central processing units have their own clocks and timing circuits for coordinating the transfer of data or instructions in the central processing unit. It is also well known that external peripheral memory devices such as disk drives, tape drives and external memory do not operate at the same high speed as the central processing unit and may require auxiliary timing means for communicating with the central processing unit. When the information in a peripheral device is to be transferred into an active or working register of the central processing unit, it must be read out of some device such as a buffer register with timing circuits of the central processing unit.
In the case of some solid state memories, the request for data or instruction causes the memory to transfer the data or instruction at the identified address location in memory. Such memory systems often preceed the actual information being transferred to the central processing unit with a ready signal or an information is on the bus signal. When such memories are employed, it has been the practice to synchronize the incoming information with the timing circuits of the central processing unit. Heretofore, it has been a desirable practice to automatically store the information from the memory in a buffer register and to generate a signal to the central processing unit that the buffer register is loaded.
High speed central processing units employ relatively large memories in which is stored instructions and data. After each instruction is processed, a new instruction is retrieved from the instruction memory and executed. The instruction from memory is processed into the computer by timing circuits which synchronize the transfer of the instruction into the instruction registers. While the computer is waiting for the next instruction, it ordinarily is capable of performing useful work; however, often there is no work to be processed before the new instruction is received. It has been suggested that buffer registers could be employed to load the next instruction to be performed in a ready or stand-by register where faster access could be obtained. While this expedient overcomes the problem associated with slow access memories, it does not enhance the access time of most solid state internal memories or the time required to transfer the instruction from a buffer register into the instruction registers.
Modern high speed central processing units perform routines which require one or more branching operations. To anticipate the next instruction for such a routine would require substantial duplication of the memory in the form of buffer instruction registers as well as logic circuitry for enabling the selection of the proper buffer instruction register.
While this problem has been explained with reference to instructions to be executed, the same problem exists when data words are transferred from memory into a working or active register of the central processing unit.
Once the desired information is located in memory, some signals such as an instruction ready or data is on the bus signal is generated which indicates that the instruction or data is capable of being transferred or is actually being transferred to a buffer register. Then and only then do the timing circuits of the central processing unit begin to synchronize the transfer of the instruction or data into active working registers of the central processing unit. Thus, in the prior art central processing units, the master clock times the transfer of information into and out of the buffer registers. It has been the practice to synchronize the asynchronous incoming signals with the synchronous master clock of the central processing unit by employing the aforementioned buffer registers.
In a typical high speed central processing unit, every instruction to be executed must be retrieved from memory. While not every instruction requires additional data from memory, on average the instructions will require at least one data word from memory. Accordingly, any decrease in the time for transferring information from an external asynchronous memory into the working registers of a central processing unit will directly increase the throughput of the central processing unit.